initial begin
a = #5 b;
end
initial begin
#5 a= b;
end
Can someone help me in understanding the difference between the above two. The one with “#5 a = b;” is blocking delay, and will delay the execution of the statements come after this statement. Is the behavior same even when “a = #5 b”. Are there any behavioral simulation artifacts?
In reply to yourcheers:
The only difference between the two is when b gets evaluated.
In the first initial construct, b gets evaluated at time 0, then there is a 5 time unit delay, and a gets assigned the value that b had at time 0. This kind of assignment is called a blocking assignment with an intra-assignment delay.
In the second initial construct, the 5 time unit delay comes before executing the statement that follows it. Then the assignment to a is made with the value of b both at time 5. Verilog still calls this a blocking assignment even though there is no intra-assignment delay. This is in contrast to a non-blocking assignment where only the update to the LHS gets delayed without blocking the process executing the statement.
Blocking assignments with intra-assignment delays is left over from very early Verilog (late 1980s) before non-blocking assignments entered the language. There is no good reason to ever use them.