Bit width casting in verilog

SystemVerilog
1

Hi,

Suppose I have a signed data type say int a;
is i do a size casting i.e, 3’(a), will it generate a signed truncated bit or not.

LRM doesnt talk about this.

2

In reply to rakesh reddy:

When changing the size, the cast shall return the value that a packed array type with a single [n-1:0] dimension would hold after being assigned the expression, where n is the cast size. The signedness shall pass through unchanged

3

In reply to dave_59:

Hi Dave,

Could you please point the same in LRM section

4

6.24.1 Cast operator