Hi,
I am trying to create a coverpoint which covers a value toggle but under a certain condition.
Here’s my code:
covergroup cg @(posedge clk);
coverpoint data iff(valid == 1'b1)
{
bins clr_to_set = (1'b0 => 1'b1);
bins set_to_clr = (1'b1 => 1'b0);
}
endgroup
I generate the following sequence of valid, data:
valid: 0 1 0 1 0 1 0
data : 0 0 0 1 0 0 0
So we have: valid with data=0, valid with data=1 and again valid with data=0
However, the coverpoint is covered at 0%
It seems that the iff condition breaks the sequence check because after the first successful hit (valid and data=0) the next time there’s no valid and after that the sequence is either reset or something like this, so the (valid and data=1) is not seen as next value for the sequence.
The SV reference says that:
value1 => value2
It represents the value of coverage point at two successive sample points, that is, value1 followed by value2
at the next sample point.
It also says:
The expression within the iff construct specifies an optional condition that disables coverage for that cover
point. If the guard expression evaluates to false at a sampling point, the coverage point is ignored.
The question is: Does this mean that even if the iff statement is false, the coverpoint is still treated as sampled, thus breaking the sequence check?
Can this be related to the simulator I’m using (VCSMX_2016.06-SP2) ?
Is it possible to make the sequence check work even when the iff statement is changing between true and false?
Thanks,
Zamfir