Bit slicing with variable width in SystemVerilog

SystemVerilog
,
1

I am trying to access certain sections of an array using the +: operator however getting the infamous [variable] is not a constant error. The only problem is, the width I would like the get from the array is changing as well.

This is the loop I have:


logic [N-1:0] a;
logic [2**N-2:0] b;
for (i = 0; i < N; i++)
    a[i] = b[(2**i)-1 +: 2**i] == {(2**i){1'b1}};

In other words, if N = 4, I want this loop to do this:


a[0] = b[0:0] == 1'b1;
a[1] = b[2:1] == 2'b11;
a[2] = b[6:3] == 4'b1111;
a[3] = b[14:7] == 8'b11111111;

Logically, I’m pretty certain that the loop I provided works however SystemVerilog doesn’t allow non-constants to be used for setting the width (after the a:).
How can I utilize the +: operator when my starting index and width are both dependent on a non-constant variable? or is there another way of doing this considering that N can be a large number.

Thanks!

2

In reply to d1r1karsy:

You can use a combination of +: operator with a mask

module top;
   parameter N  = 8; localparam N2 = 2**(N-1);
   logic [N-1:0] a;
   logic [2**N-1:0] b;

   initial begin
      b       ={8'b000001,4'b1111,2'b01,1'b1};
      for (int i = 0; i < N; i++)
          a[i]  = (b[(2**i)-1 +: N2] | ~N2'((1 << 2**i)- 1)) == '1;
      $displayb(a,,b);
      end
endmodule