Bit slicing

SystemVerilog
1

Hello,

let’s say i have two 2D bit vectors.
bit [64:0] vector_1;
bit [64:0] vector_2;

i would like to assign vector_2 to vector_1 without knowing the size of them.
something like this for example which i thought would work but doesn’t:

      req.dataWord[0 +:burst_length+1] == data[0 +:burst_length+1];

the use for this is, inside an UVM sequence, i want to use `uvm_do_with and assign a certain bit vector.
i know the size of the vector in this point in time - let’s say it’s 5 but it can be any value in the range of [1-16].
so instead of writing

      case(burst_length)
        1:
        2:
        ...

i would like to use less code and write it in a way that would match all values of burst_length (all the sizes of the vector).

any help would be much appreciated.

Thanks,
Assaf

2

In reply to assafgedalia:

Do you mean that dataWord is declared like vector_1 and data was vector_2?

How do the sizes of these arrays relate to bust_length? Is burst_length smaller than the size of the array, or do you want the result of the assignment so that dataWord is an array of size burst_length?

3

I don’t clearly understand what do you want, but maybe you are looking for something like this:


`uvm_do_with(req, {
  req.dataWord.size == burst_length;
  foreach(req.dataWord[i]) {
    req.dataWord[i] == data[i];
  }
})

Btw, using `uvm_do_with macro is not recommended.
Ref: http://verificationhorizons.verificationacademy.com/volume-7_issue-2/articles/stream/are-ovm-and-uvm-macros-evil-a-cost-benefit-analysis_vh-v7-i2.pdf

4

In reply to An Pham:

Brilliant. exactly what i was looking for.
Thanks.