Bins reduction

SystemVerilog
1

Hi All,

Please help me in reducing this bins

I have macro #define SIZE 64

I have a variable in a class as follows
 bit [`SIZE-1:0] data;

Now I want to cover that all the bits of data are atleast once set to 1… I know that I can write each bin for each position. But as the SIZE increases it becomes very much complex for me to write bins large number of bins. Please help me with some easiest way.

Similar way I want to cover that all bits of data are transitioned from 1->0 and 0->1. I need the easiest way for this also

Thanks
Anudeep

2

In reply to Anudeep J:

Hi Anudeep,
System verilog allows maximum of 64 bins only.
As per your requirement you can write a bin ike this
DATA_CP : coverpoint data {
bins all_one = 64’hffff_ffff_ffff_ffff;
}

If this bin is covered then all bits of data is 1 atleast once.

3

In reply to avpchandra:

If I do not get that value(64’hffff_ffff_ffff_ffff), then How would I know which positions are covered?

4

In reply to Anudeep J:

Hi Anudeep,
What i am conveying is you can define explicit bins which you are interested to see. Else you can directly give “option.auto_bin_max = N(maximum 64 bins)” so that implicitly it will generate N bins.

5

In reply to avpchandra:

Defining explicit bins becomes hectic when the Size keeps on increasing. With option.auto_bin_max, I have to set it accordingly based on size.

6

In reply to Anudeep J:

What you need to do is create an array of covergroups, one for each bit. See https://verificationacademy.com/forums/systemverilog/bitwise-toggle-coverage-bitvector#reply-38133