I am trying to bind a module to a VHDL generate block:
module top;
...
DUT dut();
bind dut.GENERATE_BLOCK.sub_module module2bind module2bind_inst()
endmodule
However I get the error:
** Error: Cannot bind to 'dut.GENERATE_BLOCK.sub_module'. Invalid bind target.
Shouldn't I be able to bind to VHDL "generate" blocks?
