Bind statements to VHDL generate block

SystemVerilog
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1

I am trying to bind a module to a VHDL generate block:

 
module top;

...
DUT dut();

bind dut.GENERATE_BLOCK.sub_module module2bind module2bind_inst()

endmodule

However I get the error:

** Error: Cannot bind to ‘dut.GENERATE_BLOCK.sub_module’. Invalid bind target.

Shouldn’t I be able to bind to VHDL “generate” blocks?

2

In reply to ce_2015:

There is no specification defining the interaction of SystemVerilog and VHDL. The use of bind statements into a VHDL block will be vendor dependent and your results may vary depending on which tool you are using.

For additional assistance, refer to your tool documentation or contact your vendor support team.