Bind module with assertion module with extra signals

SystemVerilog
1

I am trying to bind a module M with an assertion module AM. The port list of both these modules are not the same. I am using some of the signals of module M as input to assertion module AM along with some additional signals that are not a part of module M.

Is it possible to do this?

module M ( logic a, b, c);
endmodule

module AM ( input logic a, b, d, e);
endmodule

bind M AM bind_M_AM_inst (.a(a), .b(b), .d(some_sub_module.some_signal1), .e(some_sub_module.some_signal2)
2

In reply to Ankit Bhange:

Did you try it? Did it work? Did you get an error?

With a few more lines of code, you will have a complete environment demonstrating your requirements:


module SM ( logic d, e );
endmodule

module M ( logic a, b, c);
  wire d, e;
  
  SM sm0(.*);
endmodule

module AM ( input logic a, b, d, e);
endmodule

module testbench();
  bind M AM bind_M_AM_inst (.a(a), .b(b), .d(sm0.d), .e(sm0.e));
endmodule
3

In reply to cgales:

What I am actually doing is,

file_SM1.sv

module SM1 ( logic d, e );
endmodule

file_SM2.sv

module SM2 ( logic f, g );
endmodule

file_AM.sv

module AM ( input logic f, g, d, e);
endmodule

filelist.f
file_SM1.sv
file_SM2.sv
file_AM.sv

top_rtl.sv

module M ( logic a, b, c);
  wire d, e, f, g;
 
  SM1 sm1_inst(.*);
  SM2 sm2_inst(.*);

bind SM2 AM bind_SM2_AM_inst (.f(sm2_inst.f), .g(sm2_inst.g), .d(sm1_inst.d), .e(sm1_inst.e)); 

endmodule

It does seem to work.
I can see the assertion module being instantiated under the module it is bound to. All signals seem to be toggling fine.

If this is allowed, what does it mean? I can even bind anything to the assertion module and connect some random signals to the assertion module? In practice this is not very useful, but it seems to be allowed.

Repeating the same code but everything is together for better readability.

module SM1 ( logic d, e );
endmodule


module SM2 ( logic f, g );
endmodule


module AM ( input logic f, g, d, e);
endmodule



module M ( logic a, b, c);
  wire d, e, f, g;
 
  SM1 sm1_inst(.*);
  SM2 sm2_inst(.*);
 
bind SM2 AM bind_SM2_AM_inst (.f(sm2_inst.f), .g(sm2_inst.g), .d(sm1_inst.d), .e(sm1_inst.e)); 
 
endmodule
4

What I have done effectively is basically bind a bunch of signals with an assertion module.

5

In reply to Ankit Bhange:

You are correct in that you can bind to any signal. There is no requirement that they are ports.

The hierarchy starts at the level of the bind, so you should ideally only reference signals at that level are below to ensure that all signals exist.

However, you can start a signal path at the top level and your tool should resolve the signals, but this typically isn’t a good idea.