Bind keyword in multiple instances

SystemVerilog
1

Hi Forum,

When I tried to instantiate a TEST_TB which contains binding interface and DUT in a top TB multiple times, I am getting an error like Duplicate instance of bind found.

module DUT (input clk, bit[7:0] Addr,
            output     bit[7:0] Data);

  always @(posedge clk)
  begin
    Data = Addr + 1;
  end

endmodule

module Test (input bit[7:0] Addr, Data);

  initial
    #100 $stop;

endmodule


module CheckAddr (input clk, bit[7:0] Addr, Max);
  default clocking cb @(posedge clk); endclocking
    A1: assert property (Addr <= Max)
        else $error("Address is out of range");
endmodule
    
module DUT_TB (input bit clk, input bit[7:0] Addr, Data);

  
  DUT dut_inst (clk, Addr, Data);

  // Binds an instance of the module Test to the testbench
  bind DUT_TB Test Test_inst(Addr, Data);

  // Binds an instance of the module CheckAddr to the DUT instance
  bind DUT_TB.dut_inst CheckAddr CA_inst1(clk, Addr, Data);

  // Alternative syntax for the above
  bind DUT: dut_inst CheckAddr CA_inst2(clk, Addr, Data);


endmodule
      
module DUT_TOP;
    bit[7:0] Addr, Data;
  bit clk;

  assign #5 clk = (clk == 1'b1 ? 1'b0 : 1'b1);
  assign #10 Addr = Addr + 1;
  
DUT_TB DUT_TB1(clk, Addr, Data);
DUT_TB DUT_TB2(clk, Addr, Data);
  
  // Dump waves
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1, DUT_TB.dut_inst);
  end
  
endmodule

Error:
DUT_TOP
bind DUT_TB Test Test_inst(Addr, Data);
|
xmelab: *F,SVBDUPI (./testbench.sv,40|27): Duplicate instance ‘Test_inst’ found for target instance ‘DUT_TOP.DUT_TB1’ for bind elaborated in scope: @DUT_TOP.DUT_TB2
The existing instance got elaborated in scope: @DUT_TOP.DUT_TB1 (./testbench.sv,40|27).
xrun: *E,ELBERR: Error during elaboration (status 2), exiting.
TOOL: xrun 20.09-s003: Exiting on Jun 01, 2023 at 06:35:25 EDT (total: 00:00:00)

2

In reply to g1neela:

The problem is with your first bind statement. It tries to instantiate a test module inside every instance of DUT_TB. Since there are 2 instances of DUT_TB AND the module you are trying to instantiate the module into is the same module where the bind statement appears, it as if you are trying to place two modules with the same name within the same target module.

It doesn’t make sense to use the bind construct to instantiate a module into itself. You would just use normal module instantiation syntax.