Bind for an interface with virtual handle

SystemVerilog
1

Hi,

Can we use bind for an interface with virtual handle?
For example, below code reports error due to : i_tb.tb_inf = i_inf1;

/

/------------------------------
interface test_inf(output logic[17:0] odata,input bit idata);
 always @(idata or odata) $display("%0t :: %m :: idata=%0d  odata=%0h",$time,idata,odata);
endinterface : test_inf

//------------------------------
interface intf_bind(output logic[17:0] odata,input bit idata);
initial begin
 wait(idata ==1);  force odata ='h7FFFF;
end
endinterface : intf_bind

//------------------------------
class tb_class;
  virtual test_inf tb_inf;
endclass

//------------------------------
module top;
  bit idata[2];
  logic [17:0] odata[2];
  test_inf i_inf1(odata[0],idata[0]);
  test_inf i_inf2(odata[1],idata[1]);

  bind test_inf:i_inf1 intf_bind i_bind(odata,idata); 

  initial #10 idata[0]=1;

  initial begin
    tb_class i_tb = new();
	i_tb.tb_inf = i_inf1;
    #500 $finish;
  end
endmodule : top

**Error observed :
**Error-[ICTA] Incompatible complex type
testbench.sv, 34
Incompatible complex type assignment
Type of source expression is incompatible with type of target expression.
Mismatching types cannot be used in assignments, initializations and
instantiations. The type of the target is ‘virtual interface test_inf’,
while the type of the source is ‘interface test_inf’.
Source Expression: top.i_inf1

2

In reply to g8Grundeller:

There’s nothing wrong with your code (other than the static variable initialization of i_tb). Try any other simulator. Bind is supposed to behave exactly as if you explicitly instantiated intf_bind directly inside test_intf.

You need to move the static declaration with initialization of i_tb outside the initial block, or you need an explicit lifetime qualifier making sure you understand that initialization of static variables happens once before time 0, not when entering the begin/end block.