Bind inside generate and how to set value in a string using generate

SystemVerilog
,
1

Hello !

Have a basic macro like this


`define abc_dut_bind(HIR, NUM)\
 bind ``HIR`` abc_dut_bind_wrap abc_dut_bind_wrap_inst_``NUM`` ();

And wanted to use this macro inside the generate like this,


generate
 for (genvar j=0; j<MAX; j++) begin
  `abc_dut_bind(design_top, j)
 end
endgenerate

But get the below error saying.


 abc_dut_bind_wrap abc_dut_bind_wrap_inst_j[0:10] (); j undefined identifier.

Also, how to use generate for instance name ? for eg tried below case, but it says unable to use variable i etc…


generate
 for (genvar i=0; i<MAX; i++) begin
   assign pwire[p] = abc_dut_bind_wrap_inst_[i].xyz;
 end 
endgenerate
2

In reply to desperadorocks:

See `define macros usage | Verification Academy