Bind assertion module to different instances of RTL module with different hierarchies

SystemVerilog
,
1

Hi,

I am new to using Bind concept.

In the design, there are multiple instances of RTL module (mod3) which are at different hierarchy and for each instance the signals have different port connections.
EX:
Top.mod1_inst1.mod2_inst1.mod3.vld
Top.mod1_inst2.mod2_inst2.mod3.vld

Q1: How can I provide hierarchy names in the bind statement using for loop?
Q2: In my assertion module, should I create a array for the signal vld[2] and connect to each instance of the signal?

Currently I am using just one instance of my assertion module to bind as I want to verify all vld signal from different rtl instances at same time.

I tried to use the generate and endgenerate but it is giving me error that bind cannot be used inside the generate block.
Also, by creating the array, I couldnt bind the signals too.

Please help me with the problem.

Thanks,

2

In reply to jyothsna04:

If there are multiple instances of mod3, you can use bind to insert an assertion module into each instance

bind module3_name assertion_module am_inst(vld);

This creates two instances of the assertion module

Top.mod1_inst1.mod2_inst1.mod3.am_inst
Top.mod1_inst2.mod2_inst2.mod3.am_inst