Big-endian and Little-endian

SystemVerilog
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1

Hi all ,

Assume there is 32-bit data bus ,


Big Endian Byte Order: The most significant byte (the "big end") of the data is placed at the byte with the lowest address. The rest of the data is placed in order in the next three bytes in memory.

Little Endian Byte Order: The least significant byte (the "little end") of the data is placed at the byte with the lowest address. The rest of the data is placed in order in the next three bytes in memory.

So if I write data 32’h1234_5678 at address 0x04_00 for the 2 formats

(1) For Big-endian format the most significant byte ( 8’h12 ) will be stored at address 0x04_00 whereas the least significant byte ( 8’h78 ) will be stored at address 0x04_03 .

(1) For Little-endian format the most significant byte ( 8’h12 ) will be stored at address 0x04_03 whereas the least significant byte ( 8’h78 ) will be stored at address 0x04_00 .

My question is why is that the 32-bit data is divided into 4 - bytes before being stored ?
Why not store the entire 32-bit data at a single address 0x04_00
Does big-endian / little-endian implicitly mean data is stored in chunks of bytes internally ?

2

In reply to Have_A_Doubt:

This is a general computer architecture question. Many systems give you multiple ways of accessing memory. This article might help: