Best approach to categorize testbench into core and test-specific files

SystemVerilog
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1

Hello guys,

I’m looking for the best approach to categorize my testbench source files into Core and Test-Specific folders. My intention is to keep the Core files shared among different testbenches for various DUTs while Test-Specific files can be changes according to each DUT test requirements. There are some commonalities among the modules im testing like they all use sort of AXI protocol bus so it make sense to have shared bits in my testbench. My essential motivation is to keep source control easier and code reviews smaller for other team members.
Is there any practical guideline for this?

Thanks,
Bahman

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In reply to bahmant:

Not exactly sure what kind of advice you ate looking for. You can use SystemVerilog packages to separate your core versus test-specific classes, and put all the files required for each package in a separate folders.

3

In reply to dave_59:

Thanks Dave,

Do you think it’s a good idea to declare the class in the package in the core folder and then define it’s tasks externally in the another (test specific) folder. For example I have a scoreboard with generic body and a “CheckActual” function which can have customized implementation for each test.
My idea is to make the core a placeholder for the casual entities in the testbench and move the actual implementations (if they are not standard and can be customized) to test-specific folders.
The main inspiration to ask this question is that I’m new to systemverilog and heard about verification methodologies but i’m not sure if they recommend these practices as well or not.