Behavior of other bits of array when only one bit is set

SystemVerilog
,
1

Hi,

I have the following FSM code as part of my design:

always_comb begin
next_state = state;
a = 2'b00;
case(state)
STATE_A: ....
STATE_B: ....
         if(enable)
          a[0] = 1'b1;
......
endcase
end

What is the behavior of the other bits of the array when only one bit is changed? That is, what if the behavior of a[1] here when only a[0] is assigned a value? Is a[1] considered to be an implicitly assigned to itself such that it is equivalent to:
a[0] = 1’b1;
a[1] = a[1];

Thanks for the help.

2

In reply to gsharma1:

Only the bit you select to write is changed, the other bits are unmodified. a[1] = a[1] or a= a; for that matter is a non-operation.

But since you wrote a = 2’b00 at the beginning of the always_comb block, all bits of ‘a’ are written in every possible branch of the block, so that represents combinational logic.

3

In reply to dave_59:
Thanks dave_59!