Basic mod function with negative integer - strange result

SystemVerilog
1

Consider:


module m;
  int lv_a;
  
  initial begin
    lv_a = -4;
    $display ("lv_a: %0d mod_3: %0d", lv_a, (lv_a % 3));
  end
endmodule

Modelsim (and another sim) prints:
lv_a: -4 mod_3: -1

This is different and strange - when compared to Python/Matlab:


>>> print (-4%3)
2
>>>

Any insights please?

Thanks

2

In reply to Srini @ CVCblr.com:

FWIW - I tried an equivalent VHDL, and got matching results (as PY/Matlab). Also going by

Looks like Verilog/SV mod is really rem. Is this ambiguity in LRM?

Thanks

3

In reply to Srini @ CVCblr.com:

No, it’s ambiguity in the modulo operator itself. See Modulo - Wikipedia

4

In reply to dave_59:

Thanks, so it is floored vs. truncated. It does hurt when Matlab model is used as a reference for the unsuspecting users.

Regards
Srini