AXI Wstrb assertion

SystemVerilog
,
1

Hi,
I am writing an assertion for AXI wstrb condition.

Here is the definition from AXI spec:

A value of X on WDATA valid byte lane is not permitted when WVALID is high.

I wrote the below assertion and it is working with few issues.

Question:
In this case, I have to manually inject the X on WDATA and test it out. Is there anyway through randomization i can inject X on any 8 bits?



import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    bit clk,wvalid;
  logic [31:0] wdata=32'h100010xx;
  //logic [31:0] wdata;
  bit [3:0] wstrb;
  //logic [7:0] hello;
  logic [31:0] mod_data;
  bit ss_sel;
 default clocking @(posedge clk); endclocking
 initial forever #10 clk=!clk;
  

 
  always @(posedge clk) begin
    /*casex (wstrb)
      4'b0001: hello = wdata[7:0];
      4'b0010: hello = wdata[15:8];
      4'b0100: hello = wdata[23:16];
      4'b1000: hello = wdata[31:24];
      endcase*/
    
    for (int i=0;i<=3;i++) begin
      ss_sel <= wstrb >> i;
      mod_data[8*i+:8] <= ss_sel ? wdata [8*i+:8] : 'h00;   
      end
    end
  
  
 property p1;
   
   @(posedge clk) wvalid |-> strong (!$isunknown(mod_data)) ;
endproperty
 
  assert property (p1) $display ("Assertion passed",$time);
            initial begin
              $dumpfile ("hello.vcd");
              $dumpvars (0,top);
            end
              
 initial begin 
   repeat(100) begin 
     repeat(1) @(posedge clk) #1;  
     if (!randomize(wvalid,wstrb) with
         {wvalid dist    {1'b1:=1,1'b0:=1};
        //  wstrb dist { 1'b1:=1,1'b0:=1};
         // $onehot(wstrb);
         }) `uvm_error("MYERR", "This is a randomize error");
        end 
        $stop; 

   end  
endmodule
2

In reply to rag123:
I would do something like what I show below. Tune it to your needs. The idea is to add local variables in your initial, randomize them, and then AND?OR them as needed.


 initial begin : ini1
    logic [31:0] v_wdata;  // <---
    bit [4:0] v_select; // bit to inject error on any of 32 bits 
    // A value of X on WDATA valid byte lane is not permitted when WVALID is high.
    //  inject the X on WDATA and test it out. 
    // Is there anyway through randomization i can inject X on any 8 bits?
   repeat(100) begin :rpt1
     repeat(1) @(posedge clk) #1;  
     if (!randomize(wvalid,wstrb, v_wdata, v_select) with
         {wvalid dist    {1'b1:=1,1'b0:=1};
         {$onehot(v_select) };
        //  wstrb dist { 1'b1:=1,1'b0:=1};
         // $onehot(wstrb);
         }) `uvm_error("MYERR", "This is a randomize error");
         v_wdata= wdata | (v_select & 'X); // vselect is onehot , making that onehot bit an X
         //
         for (int i=0;i<=3;i++) begin :for1
            ss_sel <= wstrb >> i;
            mod_data[8*i+:8] <= ss_sel ? v_wdata [8*i+:8] : 'h00;    // <-----
          end : for1
        end : rpt1
        $stop;  
   end  : ini1

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to rag123:

you can find the below generic code,

`define DATA_WIDTH 32
`define STRB_WIDTH `DATA_WIDTH/4

module data_on_strobe;
  logic [`DATA_WIDTH-1:0] data;
  logic [`STRB_WIDTH-1:0] x_pos;
  
  initial begin
    data   = 'hABCD_EFAB;
    
    x_pos = $urandom_range(((`DATA_WIDTH/4)/2)-1,0);
    
    $display("x position = %0d",x_pos);
    $display("[Before] data = %0h",data);

    data[8*(x_pos) +: 8] = 'x; 
    
    $display("[After]  data = %h",data); 
  end
endmodule

Find the EDA Playground link for above example,