Avoiding inferred latches in a combinational circuit

SystemVerilog
,
1

I’m creating a behavioral description for adding numbers in sign magnitude. However, I’m getting the following errors in quartus. How can I avoid latches being created? Thanks!
ERROR:
Warning (10240): Verilog HDL Always Construct warning at LAB_2.sv(9): inferring latch(es) for variable “Y_m”, which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at LAB_2.sv(9): inferring latch(es) for variable “Y_s”, which holds its previous value in one or more paths through the always construct
Error (10166): SystemVerilog RTL Coding error at LAB_2.sv(9): always_comb construct does not infer purely combinational logic.
Info (10041): Inferred latch for “Y_s” at LAB_2.sv(31)
Info (10041): Inferred latch for “Y_m[0]” at LAB_2.sv(31)
Info (10041): Inferred latch for “Y_m[1]” at LAB_2.sv(31)
Info (10041): Inferred latch for “Y_m[2]” at LAB_2.sv(31)
Info (10041): Inferred latch for “Y_m[3]” at LAB_2.sv(31)

CODE:

module LAB_2(
input logic [3:0]A_m,B_m,
input logic A_s,B_s,op,
output logic Y_s,
output logic [3:0]Y_m
);
always_comb
begin
if(op==1) //addition
begin
if(A_s==B_s)
begin
 Y_m=A_m+B_m;
 Y_s=A_s;
end

if((A_m>B_m)&&(A_s!=B_s))
begin
 Y_m=A_m-B_m;
 Y_s=A_s;
end

if((A_m<B_m)&&(A_s!=B_s))
begin
Y_m=B_m-A_m;
 Y_s=B_s;
end
end

if(op==0) //subtraction
begin
if(A_s==B_s)
begin
if(A_m>B_m)
begin
 Y_m=A_m-B_m;
 Y_s=A_s;
end
if(A_m<B_m)
begin
Y_m=B_m-A_m;
Y_s=B_s;
end
end
else 
begin
if(A_m>B_m)
begin
 Y_m=A_m+B_m;
 Y_s=A_s;
end
if(A_m<B_m)
begin
 Y_m=A_m+B_m;
 Y_s=B_s;
end
end
end
end
endmodule
2

In reply to VIKRANT97:

Please use code tags to make your code easier to read. I have added them for you.
It would also help to indent your code based on the nesting level of if and begin/end blocks. That I’m not going to do for you.

You avoid latches by making sure there is an assignment to a variable in every possible path though your code. You are missing the case when A_m==B_m. It would be much easer to catch this if you had written your if branches with an else clause rather than two separate if’s.

if (A_m < B_m}
   // code
else
   // code for A_m >= B_m
3

In reply to dave_59:

I tried re-structuring the code to include all possible cases(including what you suggested). But I’m getting the exact same error. Is there anything else I can do? The following is my updated code:


module LAB_2(
input logic [3:0]A_m,B_m,
input logic A_s,B_s,op,
output logic Y_s,
output logic [3:0]Y_m
);
always_comb
begin
if(op==1) //addition
	begin
		if(A_s==B_s)
			begin
			Y_m=A_m+B_m;
			Y_s=A_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
			end
// When signs are not equal:
		if((A_m>=B_m)&&(A_s!=B_s))
			begin
			Y_m=A_m-B_m;
			Y_s=A_s;
			end

		else((A_m<B_m)&&(A_s!=B_s))
			begin
			Y_m=B_m-A_m;
			Y_s=B_s;
			end
	end

if(op==0) //subtraction
	begin
		if(A_s==B_s) // when signs are equal.
			begin
				if(A_m>=B_m)
					begin
					Y_m=A_m-B_m;
					Y_s=A_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
					end
				else(A_m<B_m)
					begin
					Y_m=B_m-A_m;
					Y_s=B_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
					end
			end
			
// if(A_s!=B_s) i.e. when signs are different.

		else 
			begin
				if(A_m>=B_m)
					begin
					Y_m=A_m+B_m;
					Y_s=A_s;
					end
				
				else(A_m<B_m)
					begin
					Y_m=A_m+B_m;
					Y_s=A_s;
					end
				
			end
	end
end
endmodule
4

In reply to VIKRANT97:

You should be writing your code so that every if statement has an else or else if option. Why do you have separate
if(op==1) and
if (op=0)?

5

In reply to dave_59:

I thought that since this is a behavioral description, we can describe it just like in C-programming(where this would be acceptable). However, even after having an else/else-if for every if-condition and removing some redundant code, I’m getting the same error again.


module LAB_2(
input logic [3:0]A_m,B_m,
input logic A_s,B_s,op,
output logic Y_s,
output logic [3:0]Y_m
);
always_comb
begin
if(op==1) //addition
	begin
		if(A_s==B_s)
			begin
			Y_m=A_m+B_m;
			Y_s=A_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
			end
			
// When signs are not equal:
		else if((A_m>=B_m)&&(A_s!=B_s))
			begin
			Y_m=A_m-B_m;
			Y_s=A_s;
			end

		else if((A_m<B_m)&&(A_s!=B_s))
			begin
			Y_m=B_m-A_m;
			Y_s=B_s;
			end
	end

else if(op==0) //subtraction
	begin
		if(A_s==B_s) // when signs are equal.
			begin
				if(A_m>=B_m)
					begin
					Y_m=A_m-B_m;
					Y_s=A_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
					end
				else if(A_m<B_m)
					begin
					Y_m=B_m-A_m;
					Y_s=B_s;// we can do Y_s=A_s or Y_s=B_s because A_s==B_s.
					end
			end
			
		else 		// if(A_s!=B_s) i.e. when signs are different.
			begin
			Y_m=A_m+B_m;
			Y_s=A_s;
			end
	end
end
endmodule
6

In reply to VIKRANT97:

The compiler is showing the error just before the if(op==1) line. I guess its creating a latch for the outputs just before that loop starts. However, initializing the inputs gives an error and initializing the outputs does not help either. How else can we initialize the variables o avoid the latch? Thanks!

7

In reply to VIKRANT97:

Ok, I got it to run now. I just had to initialize Y_s and Y_m just before the if(op==1). By doing this we can avoid creating latches.