In reply to haithamx15:
I'm going to use the term "bit" here to mean the bit width of the 4-state logic data type, not to be confused with the SystemVerilog 2-state bit data type.
The built-in wire nettype can be a single bit(scalar), or many bits packed into an array (vector). Nets can have multiple drivers(continuous assignments), but each bit of vector gets resolved independently using a truth table depending on the strength and built-in net type. For example, if a wire has a 1 and 0 driving a bit, the resolution of that bit is X. You can also select individual or a range of bits to read or drive.
The LRM is using the terminology atomic to describe the behavior of that scalar bit; meaning you cannot divide it into smaller pieces below a bit. User-defined nettyps are always atomic regardless of the underlying data type. You could have an 8-bit user-defined nettype where those 8-bits represent a voltage, and when there are multiple drivers, you could define the resolution to be the average value of all the drivers. It makes no sense in that case to look at the individual bits of that nettype.