Atomic Guarantees of SystemVerilog

SystemVerilog
1

Hello,

I’m new to the forum (but i did try to find a similar question) and learning SystemVerilog (simulation/verification constructs for this question only).

Coming from software background i have 1 specific question: atomic guarantees. specifically, below is a small reproducer to do an accumulation.

module automatic test;
    int sum = 0;

    task accum();
        sum++;
    endtask

    initial begin
        for (int i=0; i<10; i++) begin
            int ii = i;
            fork
                accum();
            join_none
        end

        wait(sum == 10);
        $display("sum = %0d", sum);
        $finish;
    end
endmodule

question: does SystemVerilog provide a guarantee that when 2 threads reach

sum++

statement, that there will be no side effects.
For instance, take c++, the result will be undefined (at least from the standard point of view). However, I guess (from going over Chris Spear SystemVerilog for Verification 2nd edition) that this is assumed for this (sum++). It is clear that no guarantees on the order, but for this one, i’m not sure.

Any advice on this would be really appreciated.

VK

2

In reply to vkhristenko:

The SystemVerilog LRM provides no guarantees of atomic execution (except for semaphores and mailboxes). Although it is rare to see non-atomic execution in current implementations, certain optimizations and newer hardware based simulation implementations will expose this more.

3

In reply to dave_59:

thanks! Bottom line, if one wants to be 100% accurate w.r.t. System Verilog LRM, you have to put a critical section in there around accumulator, for the example i provided.