In reply to ben@SystemVerilog.us:
Thank you for getting back to me about this. I appreciate your feedback. Unfortunately, I am unable to access the RTL code at this time. However, I am writing the sva properties to meet the requirements outlined in an IP document for a port.
Port signal specification:
signal should be treated as a STATIC input. If the value changes during operation, data corruption will occur.
It is also mentioned that signal
is independent of the clocks and thus asynchronous.
From this specification I gathered that the signal
is only able to legally change state on an edge of the system reset.