Asynchronous Signal Drive in SV class

SystemVerilog
,
1

Hi All,

How to drive signal asynchronously in system verilog class.(just like “assign” construct used in Verilog)…?

Regards,
Manoj

2

“assign” doesn’t mean asynchronous drive, it means continuous drive. You can’t do it from a class, you can only do procedural drives.

3

In reply to manoj_k86:

You need to be more explicit about the behavior you are looking for. An assign statement is just a process that waits for a change on the RHS to make an assignment to the LHS. You can create a process from within a method of a class to do something similar, but process has to call that method. It would really help to know what you are trying to achieve.

4

In reply to dave_59:

In my test-bench, I have to drive signal on DUT port synchronously or asynchronously depends on DUT mode.The clock used in drive signal is provided by DUT.So that,In some cases this DUT clock is turned-off and I have to drive signal asynchronous(continuous without any clock reference).
Looking for your response on same.

5

In reply to manoj_k86:

How about showing a self-contained example of how you would do this in a SystemVerilog/Verilog testbench without classes? Then we can show you how to do the same thing with a class based testbench.

6

In reply to dave_59:

Have a look following example :

//DUT mode change by test-bench according requirement

module test;

bit tb_clk;
bit dut_clk;

bit dut_mode;
bit [7:0] data_in,asyn_data_in,syn_data_in;

bit clk_on;

assign data_in = clk_on ? syn_data_in : asyn_data_in;

//Synchronous
always @(posedge dut_clk)
begin
syn_data_in = 8’hff; //syn_data_in drive logic
end

//Asynchronous
assign asyn_data_in = 8’h00;//asyn_data_in drive logic

always @(posedge tb_clk)
begin
if(dut_mode)
clk_on = 1’b1;
else
clk_on = 1’b0;
end

initial
begin
#10;
dut_mode = 1’b1;
#50;
dut_mode = 1’b0;
#50;
$stop;
end

initial
begin
tb_clk = 1’b0;
forever #5 tb_clk = ~tb_clk;
end

dut tb_dut(
.clk_in(tb_clk),
.dut_mode(dut_mode),
.data_in(data_in),
.clk_out(dut_clk)
);

endmodule : test

//DUT
//requirement
//“data_in” port drive with reference of “clk_out” when available otherwise drive continuous.

module dut(
input clk_in,
input dut_mode,
input [7:0] data_in,
output reg clk_out
);

always @(posedge clk_in)
begin
if(dut_mode)
//output clock generation logic
else
//disable output clock
end

always @(posedge clk_in)
begin
// data_in related logic
end

endmodule

How to implement above verilog test-bench logic in system verilog class based test-bench…?
7

In reply to manoj_k86:

Hi Manoj,
How about the following code?

class test;
bit tb_clk;
bit dut_clk;
 
bit dut_mode;
bit [7:0] data_in,asyn_data_in,syn_data_in;
 
bit clk_on;

function new ();
    asyn_data_in = 8'h00;
endfunction

task run
    fork
        drive_syn_data_in;
        drive_clk_on;
        drive_data_in;
    join_none
endtask

task drive_syn_data_in;
    forever begin
        @(posedge dut_clk);
        syn_data_in = 8'hff;
    end
endtask

task drive_clk_on;
    forever begin
        @(posedge tb_clk);
        if(dut_mode)
            clk_on = 1'b1;
        else       
            clk_on = 1'b0;
    end
endtask

task drive_data_in;
    forever begin
        if (clk_on)
        data_in = syn_data_in;
        else 
        data_in = asyn_data_in;
        #1;
    end
endtask
endclass