In reply to KranthiDV:
Your issue is your misunderstanding of the until property operator.
An until property of the non-overlapping form (i.e., until, s_until) evaluates to true if property_expr1 evaluates to true at every clock tick beginning with the starting clock tick of the evaluation attempt and continuing until at least one tick before a clock tick where property_expr2 (called the terminating property) evaluates to true.
Consider this example: https://www.edaplayground.com/x/m2XY
ap1: assert property(@ (posedge clk) $rose(a) |=> b ##1 a until c);
The
until requires that the property
(b ##1 a) repeats and must be true at every cycle.
See the images below.
What you need is the concatenation of a sequence and a property.
Thus, the following is illegal:
property P_illegal; a_sequence ##1 a_property; endproperty : P_illegal
This capability is introduced with the followed-by operators #-# and #=# that concatenates a sequence and a property. The followed-by operators are of the following forms for the definition of a property:
[1] sequence_expr #-# property_expr // concatenation with zero cycle delay
| sequence_expr #=# property_expr // concatenation with one cycle delay
assumption_a: assume property (@(posedge clk)disable iff (rst)$rose(req) |=>
$fell(req)#-# !(req) until $fell(rsp) );
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
1) SVA Package: Dynamic and range delays and repeats https://rb.gy/a89jlh
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Understanding the SVA Engine,
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Reflections on Users’ Experiences with SVA, part 1 and part 2
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SUPPORT LOGIC AND THE ALWAYS PROPERTY
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SVA Alternative for Complex Assertions
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SVA in a UVM Class-based Environment
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SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
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