Associative arrays

SystemVerilog
,
1

I just want to make sure I have got this correct as I am going to implement something based on this.
When I overwrite an entry in an associative array, I see that the new value is rejected, which is what I am looking for.

The following is the code I have tried:

module one;
  int Q[int] ;
  int x, y;

  initial begin
    Q[1] = 1;
    Q[2] = 2;
    Q[3] = 3;
    Q[3] = 4;
    $display ("%d %d %d", Q[0], Q[1], Q[2]);
  end
endmodule

The following is the output:

         0           1           2

At least I am not able to find anything in LRM that describes this behaviour

2

In reply to verif_learner:

What happens when you print Q[3], which is the value you are changing?

3

In reply to cgales:

In reply to verif_learner:
What happens when you print Q[3], which is the value you are changing?

Sorry about that. I used Q[0] which is actually no existent (until I used it in display statement) and assumed I have displayed all 3 entries.

I checked it again. The latest entry takes effect.
So, I have to check using exists() function to make sure that I don’t overwrite it if it is already present (which is what I need actually)