hello everyone,
i have tried to implement associative array of queue,but its throwing simulation error like Illegal assignment to type ‘bit[31:0]$’ from type 'reg signed
code:
class associative;
bit [31:0]associative_arr[*][$];
int index;
task run();
for(int i=0;i<10;i++) begin
index=$urandom_range(0,10);
associative_arr[index]=$random;
$display("index=%0d\t,associative_array=%0h",index,associative_arr[index]);
end
endtask
endclass
module top();
associative a;
initial begin
a=new();
a.run();
end
endmodule
is wrong. You are trying to assign a random number to a queue. You need to treat associative_array[index] as a queue.
class associative;
bit [31:0]associative_arr[int][$];
int index;
task run();
for(int i=0;i<10;i++) begin
index=$urandom_range(0,10);
associative_arr[index].push_front($urandom);
$display("index=%0d\t,associative_array=%0p",index,associative_arr[index]);
end
endtask
endclass
module top();
associative a;
initial begin
a=new();
a.run();
end
endmodule
you should be using $urandom instead of $random to take advantage of SystemVerilog’s random stability and seeding functionality.
Associative arrays should have a declared index type and not use a wildcard index. This let you use a number of other SystemVerilog features like foreach loops.