Associative array mapping in SystemVerilog

SystemVerilog
1

Hi,
My code produces an output format in the form of Tcl file that defines an associative array
The current output is:

array set active {
0  {0 100}
35 {100 200}
0  {200 300}
35 {300 400}
}

The keys of the array is particular register value. As you can see the keys are repeating I want to map the keys of the array to something like below:

array set active {
a-0  {0 100}
b-0 {100 200}
a-1  {200 300}
b-1 {300 400}
}

where a & b will be the string and 0 and 1 will be the incremental index every time the same key is repeating so that I can avoid the duplicate index being overwritten by the last value I want to get all the values.
Please let me know if there is any method to do within the SystemVerilog model.

2

In reply to random_coder:

You can create an associative array to keep track of the number of times you’ve seen each key.

int keyCount[int];

Then in your code you can increment the keyCount each time use see a key repeated.

if(!keyCount.exitsts(key) 
  keyCount[key] = 0; // first time key has been seen
else
  keyCount[key]++;

We would need to see the code that generates your output to one the bet way of integrating it
Creating an alphabetic sequence of key names is not so simple if you are expecting more than 26 keys. Can you use 0-0, 0-1, etc?

3

In reply to dave_59:

Hi Dave,
Yes numeric-IDs will also do the work.I just want to avoid the duplicate keys so that I am able to get all the values because the values you see with respect to the keys are start_time and end_time of every register value window.


always @(reg)
begin
start_time <= $time;
prev_value <= reg_value;
$fdisplay(fd, "  %d {%0t %0t}", prev_value,start_time,$time);

Every time the reg value changes I want to write the key=“prev_value” {start_time end_time} in associative array named as “active”. But since the reg value is repeating sometimes I want to map the key as mentioned above so that I get timing of all the windows. Well I do not have more than 26 keys and since I am bit of beginner in SystemVerilog I would like to learn the logic for both alphabetic sequence eg: a-0, b-0 , a-1 as well as numeric ids eg: 0-0, 1-0, 0-1, etc.

4

In reply to random_coder:

For the numeric ids, you can do

int keyCount[int];
always @(reg) begin
  start_time <= $time;
  prev_value <= reg_value;
  if(!keyCount.exitsts(prev_value) 
    keyCount[prev_value] = 0; // first time key has been seen
  else
    keyCount[prev_value]++;
  $fdisplay(fd, "  %0d-%0d {%0t %0t}", prev_value,keyCount[prev_value],start_time,$time);

For the alphabetic ids, you need one more associative array

int keyCount[int];
byte Id="a",AlphaId[int]
always @(reg) begin
  start_time <= $time;
  prev_value <= reg_value;
  if(!keyCount.exitsts(prev_value) begin
    keyCount[prev_value] = 0; // first time key has been seen
    AlphaId[prev_value] = Id++;
  end
  else
    keyCount[prev_value]++;
  $fdisplay(fd, "  %c-%0d {%0t %0t}",AlphaId[prev_value],keyCount[prev_value],start_time,$time);
5

In reply to dave_59:

Hi Dave,
That worked. But I am facing a small issue since some of the prev_value is “X” which makes it an invalid index of an associative array. With numeric ids it was still not a problem as I was performing unset from Tcl script to remove the contents with Index “X”. But with alphabetic sequence it is causing an issue in the sense that index values mapping starts from “b” instead of “a” and I assume it is because the first index it encounters is “X”.

Is there any way to delete the “X” index from SystemVerilog model itself so that the index mapping can start from “a”. There is delete function in associative array. Will that solve the issue. If that solves my issue can you please let me know in which part of the code do I need to put it.