Hi All ,
Generally interface is passed as part of module port_list and within the module , variables declared within the interface are assigned in the module.
I tried the reverse in below code
interface intf ;
// Assigns the module level variables .
function automatic void ASSIGN( input logic [4:0] ip_a , input logic [3:0] ip_b );
csr.reg_a = ip_a ;
csr.reg_b = ip_b ;
endfunction
endinterface
module csr ;
logic [4:0] reg_a ;
logic [3:0] reg_b ;
intf intf0 ();
endmodule
module top ;
csr CSR();
initial begin
CSR.intf0.ASSIGN( 10 , 4 );
$display(" reg_a == %0d " , CSR.reg_a );
$display(" reg_b == %0d " , CSR.reg_b );
end
endmoduleI observe that the code works but I do not quite get the following ::
How is that there is No compilation / elaboration time error when accessing csr.reg_a / csr.reg_b within the interface ?
Does an interface have an implicit access to all the variables of the module within which it's instantiated ?
