Assign real to integral - when real exceeds integral range

SystemVerilog
1

The LRM says (6.12.2): “Real numbers shall be converted to integers by rounding the real number to the nearest integer, rather than
by truncating it. Implicit conversion shall take place when a real number is assigned to an integer.”

But I have the impression that this holds only when the Real number does not exceed the representable range of the integral number?

For example:

real r=200;
bit signed [7:0] b;
b = r;   // <--- b equals -56

I do not see how this is according the LRM, isn’t the nearest integer 127? It seems the tool is just wrapping, or copying the respective bits.
But what happens if the IEEE754 Real exponent is also involved?

Is it defined what happens when a real is assigned to an integral, where the real is outside the representable range of the integral?

2

I believe section 6.12.2 it just referring to the fractional part of a real number.

Unfortunately, the Verilog LRM does not provide checking when an integral value exceeds the maximum representable range of the target variable. It will just silently truncate the MSB bits.