Assign parameter with $bits()

SystemVerilog
,
1

Hi,

I’m trying to assign localparam with $bits() on a struct inside a union inside an interface from my ports.
The motivation for that is to make my module robust to width changes in the irq_bus inside the interface.

It doesn’t seems to work.

Is it possible to do that in any other way?
meaning, can I change bus width inside interface and pass that info to my module at compilation stage?


module interrupts_serializer
    (
        output        var logic [IRQ_SERIALIZED_DATA_WIDTH-1:0] data,
        output        var logic                                 valid,
        interrupts_if                                           irq_if,
        input         var logic                                 sys_clk,
    );

    // THIS LINE FAILS....
    localparam integer IRQ_BUS_WIDTH = $bits(irq_if.irq_union.irq_bus); 
    localparam integer DETECTION_GRANULARITY        = 128;
    localparam integer IRQ_BUS_DETECTION_RESIDUE    = IRQ_BUS_WIDTH % 4;
    localparam integer IRQ_BUS_TRANSMIT_RESIDUE     = IRQ_BUS_WIDTH % 8;

endmodule

import general_pkg::*;
interface interrupts_if;
    
    typedef struct packed {
            logic                         pvt_sensor_threshold_irq;
            logic [NUM_OF_BANDS-1:0]      mac_phy_gp_if_irq ;
            logic [3:0]                   external_irq_out_synced;
            logic                         shram_addr_irq;
            logic [NUM_OF_BANDS-1:0]      ulpr_report_fifo_not_empty_irq ;
            logic [1:0]                   pcie_irq;
        } interrupts_struct;

    typedef union packed {
        interrupts_struct irq_struct; 
        logic [$bits(interrupts_struct)-1:0] irq_bus;
    } interrupts_union;
    
    interrupts_union irq_union;
endinterface
2

In reply to yakir_mishli:

See Parameterizing the Bit Widths of fields in a packed struct so that modules can infer bit width if used in port map - virtual interface - interface - compile time configured struct bit width | Verification Academy