Assign delay behavioural differences

SystemVerilog
,
1

Hi

Can anyone explain why the following 2 pieces of code behave differently?

reg a;
reg b;
assign #1 a = b;

wire a;
reg b;
assign #1 a = b;

2

Can you elaborate on the difference you are seeing?

3

In reply to ceesam:

Reg type is not a legal lvalue and cannot be used on left side of continuous assignments!(When used with .v file extension[Verilog]). However same piece of code will work when used with .sv file extension[SystemVerilog], in that case there’s no difference between both usage.

4

In reply to MayurKubavat:

In reply to ceesam:
Reg type is not a legal lvalue and cannot be used on left side of continuous assignments!(When used with .v file extension[Verilog]). However same piece of code will work when used with .sv file extension[SystemVerilog], in that case there’s no difference between both usage.

Changing the file extension to sv does not resolve the difference issue. If the left hand of the assignment is of type reg then the output is X.

5

In reply to ceesam:
A continuous assignment to a reg variable should have been illegal in Verilog, so I assume that everything is being run in SystemVerilog.
Again, can you elaborate? What should the value be, and when should it change. Can you provide a small self-contained example that shows the difference you are seeing?

6

In reply to dave_59:

In reply to ceesam:
A continuous assignment to a reg variable should have been illegal in Verilog, so I assume that everything is being run in SystemVerilog.
Again, can you elaborate? What should the value be, and when should it change. Can you provide a small self-contained example that shows the difference you are seeing?

I would have thought illegal as well but it does not flag as an error/warning in the simulator (Cadence). Nothing in the LRM regarding this. I am simulation in SV.

module rtl ();

  reg       tmp1;
  reg       tmp2;
  wire      tmp3;
  wire      tmp4;
  
  assign #1 tmp1 = en;
  assign    tmp2 = en;
  assign #1 tmp3 = en;
  assign    tmp4 = en;

endmodule


module tb;

  rtl dut();

  initial begin

  dut.en=1;
  #5;
  dut.en=0;
  #4;
  dut.por=1;
  #1;
  
  end

endmodule
7

In reply to ceesam:
If you are simulating in SV, then there should be no errors.

Your example has two typos:

  1. You forgot to declare
    en     as a
    reg    . And since you are using SystemVerilog, I recommend replacing
    reg     with
    logic
  2. You have
    dut.por     instead of
    dut.en

I see no differences in behavior between the assignments to the wire versus the reg. I do a difference between the assignments with no delay versus the assignments with a delay of #1. The assignments with a delay will be ‘x’ for 1 time unit.