Assertions system verilog - question on $changed concurrent assertion

SystemVerilog
1

One of the assertions I’m using doesn’t seem to print anything (either PASS or FAIL), not sure what’s wrong but I’m kinda stuck, need your inputs…
I’m a beginner to assertions
Condition: As soon as we notice a change in ‘sig_a’, within few clock (next clock to 30th clock cycle) cycles later ‘sig_b’ should change.

property name(clk,rst_n,sig_a,sig_b);
  @(posedge clk) disable iff (!rst_n)
  $changed(sig_a) |-> ##[1:30] sig_b;
endproperty

Test :

 assert name(clk,rst_n,sig_a,sig_b
    $display("time:%t assertion passed ", $time);
  else
    $display("time: %t assertion failed ", $time);

Also checked the simulation time. It is alive 70 clock cycles after change detected on ‘sig_a’

Please advise on what could be wrong

2

In reply to shashankadimulam:

Should work, assuming that the change occurred some time after the first cycle.
To take into account the very first cycle, you would need:


1'b1 ##1 $changed(sig_a) |-> ##[1:30] sig_b;

This is because a $change, $past requires a past value that is set at time 0 to the initial of the variable.
Also, does your testbench have a change in sig_a?

Ben systemverilog.us

3

In reply to ben@SystemVerilog.us:

I modified and it doesn’t seem to work. Change happens on the sig_a at some random time, but as soon as this change is detected, sig_b should go high in the from 10:30 clock cycles.

I’m not sure why nothing gets printed. If the assertion is not true, at least it should print the fail statement, right?

Can you please advise on what’s wrong as I’m literally confused.
Thank you so much

4

In reply to shashankadimulam:
One can be tricked by speed reading, as I failed to notice that you declare an immediate assertion instead of a concurrent assertion. Specifically, you had


assert name(clk,rst_n,sig_a,sig_b
$display("time:%t assertion passed ", $time); ..

//It should have been 
assert property (name(clk,rst_n,sig_a,sig_b))
$display("time:%t assertion passed ", $time);

I am surpised that your compiler did not pick this up as an error.

Below is code with a quick testbench. TO minimize my mistakes, I use the following tools:

  • https://www.phraseexpress.com It is an Autotext and Text Autocompletion in any application and allows me to include boilerplate templates for SystemVerilog including a quick testbench.
  • A quick testbench for my assertions. The testbench shown below was generated with my template using PhaseExpress; you define what is in the template.
  • Visual Studio Code https://code.visualstudio.com A not too bad SystemVerilog editor that understands SystemVerilog and SVA. It is free, includes the syntax, and a “reindent lines”.
    Of course, this editor does not have all the bells and features of commercial editors, but ti is not too shabby!

import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
  timeunit 1ns;     timeprecision 100ps;    
	bit clk, a, b, rst_n;  
	default clocking @(posedge clk); endclocking
    initial forever #10 clk=!clk;  
    property p_ab (clk,rst_n,sig_a,sig_b);
        @(posedge clk) disable iff (!rst_n)
        $changed(sig_a) |-> ##[1:2] sig_b;
        endproperty
        
        ap_ab: assert property (p_ab(clk,rst_n, a, b) )
             $display("time:%t assertion passed ", $time);
        else
             $display("time: %t assertion failed ", $time);

    
    initial begin 
       bit va, vb, vc; 
      repeat(200) begin 
        @(posedge clk);   
        if (!randomize(va, vb, vc)  with 
        { va dist {1'b1:=1, 1'b0:=3};
          vb dist {1'b1:=1, 1'b0:=4}; 
          vc dist {1'b1:=10, 1'b0:=1};      
      }) `uvm_error("MYERR", "This is a randomize error")
       a <= va; 
       b <= vb;
       rst_n <= vc; 
    end 
    $stop; 
  end 
endmodule
// simulation 
time:                1500 assertion passed 
# time:                4100 assertion passed 
# time:                 4700 assertion failed 
# time:                4900 assertion passed 
# time:                5900 assertion passed 
# time:                 6500 assertion failed 
# time:                 9700 assertion failed

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  1. Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
    FREE BOOK: Component Design by Example
    … A Step-by-Step Process Using VHDL with UART as Vehicle
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5

In reply to ben@SystemVerilog.us:

Thank you so much Ben.

Following doesn’t seem to work. I might’ve made a small error, not able to understand. There are bunch of fails before it passes. I just want to know if this passes or fails for the entire simulation.

interface sample ;
 //------------------------------------------
 // Signal Instantiation 
 //------------------------------------------
 logic x;
 logic clk;
 logic rst_n;
 logic y;
 logic z;



property name_1(clk,x,y);
  @(negedge clk)   
  $rose(x) ##[10:50] y;
endproperty

Reset_test_dmgr :
  assert property(name_1(clk,x,y))
    $display("time:%t assertion passed -- first, pmsb_side_rst_b", $time);
  else
    $display("time: %t assertion failed -- first, pmsb_side_rst_b", $time);

property name_2(clk,z);
  @(negedge clk) 
  $rose(z);
endproperty

Reset_test_dmgr_punit : 
  assert property(name_2(clk,z))
    $display("time:%t assertion passed -- second", $time);
  else
    $display("time: %t assertion failed -- second", $time);

endinterface:
6

In reply to shashankadimulam:
You definitely need to understand the SVA concepts of vacuity with antecedents and consequents.
Your assertions are poorly written. Before answering your questions,
I would like you to express your requirements in English, and explain to me your understanding of vacuity, and then rewrite the assertions

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

See Paper: 1) VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.

7

In reply to ben@SystemVerilog.us:

I apologize for the confusion. I’ll pick up these concepts as suggested

My requirements:
At some point in time ‘sig_a’ transitions from 0->1 and stays there. Within say ‘x’ clock cycles, ‘sig_b’ should make a transition from 0->1 (all wrt clk and they initially start at ‘0’). In a similar fashion, bunch of other signals get triggered (more like a chain reaction).

I’m planning to write an assertion which fails if such transitions won’t occur according to the spec, otherwise they just move on. I would like to write them in a way that it just FAILS when things don’t happen according to the transition diagram.

Thanks a lot.

8

In reply to shashankadimulam:

assertion which fails if such transitions won’t occur according to the spec, otherwise they just move on. I would like to write them in a way that it just FAILS when things don’t happen according to the transition diagram.

That is exactly the purpose of an assertion!
An assertion can be written in many ways, including SV code; SVA is just a way to more easily express the requirements, but it has restrictions.

Again, do the homework I suggested. Also read my papers

See Paper: 1) VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy
2) http://systemverilog.us/vf/SolvingComplexUsersAssertions