Assertions in system verilog

SystemVerilog
,
1

Hi …
i tried to execute bleow assertion code .

  1. at time 20ns a=1,b=0. has to fail assertion
    but in log file shows like assertion fails at 25ns
    can anyone please explain why it is showing error at 25ns instead of 20ns?

[5] a=0 b=1
“testbench.sv”, 23: tb.unnamed$$_3: started at 5ns failed at 5ns
Offending ‘(a & b)’
[10] a=1 b=1
[15] a=1 b=1
[20] a=1 b=0
[25] a=1 b=1
“testbench.sv”, 23: tb.unnamed$$_3: started at 25ns failed at 25ns
Offending ‘(a & b)’
…

example :

 module tb;
      bit a, b;
      bit clk;
 
      always #5 clk = ~clk;
 
      initial begin
          for (int i = 0; i < 10; i++) begin
              
              #2 a = $random;
             #3 b = $random;
             $display("[%0t] a=%0b b=%0b", $time, a, b);
          end
        $dumpfile("dump.vcd");
        $dumpvars;
          #50 $finish;
      end
 
    
    assert property (@(posedge clk) a & b);   
 
  endmodule
2

In reply to kathoju:

Your assertion will only check a&b on the positive edge of clk. That occurs at times 5, 15, 25, etc. Concurrent assertions use sampled values of variables which are the values they had at the beginning of the current time step (it’s the same as the values they had end the end of the previous time step). At the beginning of time 25, b is still 0. Your $display statement is show the value they have after the beginning of the time step. Look at your waveform (move $dump tasks to the beginning of the initial block).

3

In reply to dave_59:

Thank you very much sir