Assertions

SystemVerilog
,
1

Hello,
my qstn is:
I have written the assertion:
property p1;
@(posedge PCLK) fell(TBIT) |-> [1:] (@(posedge TBIT)1) [1:$] (@(posedge ENS));

     endproperty

      but it gives error [SVA-CDNAISO]: Clocks delay donot agree in sequence.

Thanks and regards,
raman

2

hi,
maybe try:

//after TBIT de-asserts TBIT should eventually assert and then ENS should eventually be high

@(posedge PCLK) $fell(TBIT) |-> TBIT[->1] [1:$] ENS);