I have wrote below assertions for practice example. What i found was Passing and Failing display statement is getting printed for the same time stamp. I would like to understand this behaviour.
module svafunc;
logic clk;
logic a,b,c,d,e;
logic result=0;
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
a=0;b=0;c=0;d=0;e=0;
#3 c=1;
#7 a=1;c=0;d=1;
#8 a=0;b=1;d=0; e=1;
#15 b=0;e=0;
end
sequence ab;
(a ##1 b);
endsequence
sequence cde;
(c ##1 d ##1 e);
endsequence
within_construct : assert property (@(posedge clk) ab within cde)
begin
result=1;
$display("time=%0d assertion passed",$time);
end
else
begin
result=0;
$display("time=%0d assertion failed",$time);
end
endmodule
You have a pass and a failure because you are showing at time 25 the results of
two attempts.
The assertion that was attempted at time 15 passed at time 25.
The assertion that was attempted at time 25 failed at time 25.
// Those are the sampled values
t= 15 a=1, b=0, c=0, d=1, e=0
t= 25 a=0, b=1, c=0, d=0, e=1
“testbench.sv”, 34: svafunc.within_construct: started at 25ns failed at 25ns
Offending ‘c’
time=25 assertion failed
time=25 assertion passed
module svafunc;
logic clk;
logic a,b,c,d,e;
logic result=0;
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
a=0;b=0;c=0;d=0;e=0;
#3 c=1;
#7 a=1;c=0;d=1;
#8 a=0;b=1;d=0; e=1;
#15 b=0;e=0;
end
always @(posedge clk)begin
$display("t=%t a=%b, b=%b, c=%b, d=%b, e=%b",
$realtime, $sampled(a), $sampled(b), $sampled(c), $sampled(d), $sampled(e));
end
sequence ab;
(a ##1 b);
endsequence
sequence cde;
(c ##1 d ##1 e);
endsequence
within_construct : assert property (@(posedge clk) 1|-> ab within cde)
begin
result=1;
$display("time=%0d assertion passed",$time);
end
else
begin
result=0;
$display("time=%0d assertion failed",$time);
end
initial #199 $finish;
endmodule