How can i write assertion for checking the wrap boundary for WRAP4 and FULLWORD transfer.
In reply to fuwad khan:
How can i write assertion for checking the wrap boundary for WRAP4 and FULLWORD transfer.
Write your various requirements chunks in English, and then the translation into an assertion will be obvious.
Ben Ben@systemverilog.us
i am not getting how to correlate that thing with the code.
In reply to fuwad khan:
i am not getting how to correlate that thing with the code.
You mean you don’t understand your requirements. If so, you’re in trouble!
Dig into your requirements, and not the implementation.
Writing assertions based on implementation is useless and deceitful.
Write in English a sample of the requirements. Requirements are sometimes expressed with timing diagrams.
Ben Ben@systemverilog.us
In reply to fuwad khan:
Hi Fuwad,
You can do something like this:
property p1;
@(posedge hclk)
((haddr[3:2] = 2’b00) |-> (wrap4_boundary_location = 0)) | // No wrap
((haddr[3:2] = 2’b01) |-> (wrap4_boundary_location = 1)) | // Wrap at beat 1
((haddr[3:2] = 2’b10) |-> (wrap4_boundary_location = 2)) | // wrap at beat 2
((haddr[3:2] = 2’b11) |-> (wrap4_boundary_location = 3)) // warp at beat 3
endproperty
assert property(p1);
In reply to sunils:
Your property syntax is incorrect. You should just write multiple assertion statements.
Also, the antecedent needs more preconditions. Thus, assuming that these are the specs:
ap_wrap4_00: assert property(@(posedge hclk)
( cond && (haddr[3:2] = 2'b00) |-> (wrap4_boundary_location = 0)) | // No wrap);
// cond is the timing control (or condition) that allows the assertion to trigger.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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In reply to ben@SystemVerilog.us:
Try this!
//Address Check for WRAP4 Word
property wrap4_size2_addr_p;
@(posedge HCLK) disable iff(!HRESETn)
(HTRANS == 3) && (HBURST == 2) && (HSIZE == 2) && ($past(HTRANS, 1) != 1) && ($past(HREADY, 1))
|->
((HADDR[3:2] == ($past(HADDR[3:2], 1) + 1)) && (HADDR[31:4] == $past(HADDR[31:4], 1)));
endproperty