I have something like this to check SSC tolerance, please let me know if there is another way to do it.
property p_time(real tolerance, logic clk);
realtime v_t1, v_t2, v_hi, v_lo, v_diff;
disable iff(rst)
@(posedge clk) (1, v_t1=$time) ##0 @(negedge clk) (1, v_t2=$time, v_hi=v_t2-v_t1) ##0 @(posedge clk) (1, v_lo=$time-v_t2) ##0 v_lo/(v_lo+v_hi) >=0.5-tolerance && v_lo/(v_lo+v_hi) <=0.5+tolerance;
endproperty
ap_time: assert property(p_time(0.01,clk));