Assertion with variable delay and clock cycles

SystemVerilog
,
1 
sequence s;
  int st = st1+14;
  $rose(s1) ##1 (~s2 && st>0, st--)[*] 
endsequence
 
property p_block;
  @(posedge clk) disable iff (!rst)
 
     s  |-> ##1  $fell(s3);
endproperty
 
 
I have requirement where as soon as s1 gets asserted s2 should not be asserted for n clock cycles (where, n is variable changing) after that s3 gets de-asserted. What is better way to model the assertions
2

In reply to tejasakulu:
I assume that s1, s2, s3 at variables of type bit, and n is of type int.
Use my SVA Package: Dynamic and range delays and repeats
at SVA: Package for dynamic and range delays and repeats | Verification Academy



import uvm_pkg::*; `include "uvm_macros.svh"
import sva_delay_repeat_range_pkg::*;
module top;
  bit clk, s1, s2, s3;
  int n=3;

  initial forever #10 clk = !clk;
/* From the package
    sequence sq_rpt_simple_count(sq, count);
      int v=count;
      (1, v=count) ##0 ( v>0 ##0 sq, v=v-1) [*1:$] ##0 v<=0;
    endsequence    // sq_rpt_simple_count */
// I have requirement where as soon as s1 gets asserted s2 should not be asserted for n clock cycles
// (where, n is variable changing) after that s3 gets de-asserted. What is better way to model the assertions
  ap_s1s2s3: assert property(@ (posedge clk)
                           $rose(s1)  |->  sq_rpt_simple_count(!s2, n) ##1 !s3 );
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
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