Assertion type

how to write assertion for particular timing assertion for example serial clock is high when negaedge of serial data signal within 4us

In reply to ramDV:

Analyze the algorithm that you defined:
At negedge of serial data signal, you store the value of the current time.

At posedge of serial clock is high, you compute the value of the current time - stored time and compare that to the 4us.

Given this and a bit of knowledge of SVA or straight systemverilog, you should be able to write an assertion.

If that is too difficult, study Svg, sva.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy

In reply to ben@SystemVerilog.us:

hi ben,

I wrote like

property p1(time_period);
real time current_time;
@(negedge sda) (current_time=$realtime) |-> scl (time_period<= $realtime-current_time);

endproperty

A: assert_property(p1(4ns));


// At negedge of serial data (sda) signal, you store the value of the current time.
// At posedge of serial clock (sclk) is high, you compute the value 
//    of the current time - stored time and compare that to the 4us.

property p1(realtime time_period);
  realtime current_time; // corrected 5/26
  @(negedge sda) (1,current_time=$realtime) |-> 
                       @(posedge sclk) (time_period<= $realtime-current_time);
endproperty
ap_p1: assert_property(p1(4ns));

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy

In reply to ben@SystemVerilog.us:

when im trying to this same property getting the below error:

iilegal assignment to current_time in SVA expression

In reply to ramDV:

In reply to ben@SystemVerilog.us:
when im trying to this same property getting the below error:
iilegal assignment to current_time in SVA expression

For local variable inside a property value can be assigned on the completion of any (sub-)sequence & the syntax is (SEQ_A, var=value)

 
property p1(realtime time_period);
  realtime current_time; 
  @(negedge sda) (1,current_time=$realtime) |-> 
                       @(posedge sclk) (time_period<= $realtime-current_time);
endproperty
ap_p1: assert_property(p1(4ns));

Regards,
Shanthi

In reply to ramDV:

@(negedge sda) (1,current_time=$realtime) |-> 
                       @(posedge sclk) (time_period<= $realtime-current_time);

add this line.

In reply to juhi_p:

In reply to ramDV:

@(negedge sda) (1,current_time=$realtime) |-> 
@(posedge sclk) (time_period<= $realtime-current_time);

add this line.

still getting same error

In reply to ramDV:

What type of error are you getting? Compilation or simulation?
Code looks OK.

In reply to ramDV:

It was working fine at my end. what is error that you are facing?

In reply to juhi_p:

In reply to ramDV:
It was working fine at my end. what is error that you are facing?

Regarding previous post I was looking in i2c protocal start condition setup time but it shud occur only once
hi juhi,
I hv one more query
how to get benum class random varibale in module.

requement is: i need to write assertions to for particular address mode and these address mode is randomizing in class this randomization variable i need to get in module file

In reply to ramDV:
Can you please elaborate more so that I can help you? Question is not clear to me.

In reply to juhi_p:

In reply to ramDV:
Can you please elaborate more so that I can help you? Question is not clear to me.

juhi,

im writing a assertions for i2c vip so in that we have only two signals scl and sda. we will have address modes and speed modes in that these are internal variables we hvae taken in sequence how to get these enum variables in my assertion module.