Assertion with two different clocks

SystemVerilog
1

Is there a way we can switch the clock(second) of the assertion checking in the middle once the checking start with the first clock

lets says I have four signals
cs_n, sck,clk_in,ch_sel

Here is the sequence wrt clk_in we want to write a assertion

  1. cs_n falls
  2. then sck starts toggling
  3. with in 5 sck cycles ch_sel goes high

if we write something like this it will work on clk_in and is there a way for the tool to tell that first work on clk_in and switch to sck once it starts toggling?

ap_ch_sel_check : assert property(
@(posedge clk_in) $fell(cs_n) |-> ##2 sck |-> ##[0,10] ch_sel;

2

In reply to gv_bing:

Is this correct? cs_n, sck wrt clk_in and ch_sel is checked between [0,5] clocks of sck

ap_ch_sel_check : assert property(
@(posedge clk_in) $fell(cs_n) |-> ##2 sck |-> (@(posedge sck) !cs_n |-> ##[0:5] ch_sel));