can anyone share the document in which it consists of assertion trigerring based on change in variable rather than clock.i would be thankful for it
In reply to venky970:
Isn’t @(variable==some_value) a clocking event? SVA is event-based; usually, that event is a clock edge, but it does not have to be. Thus,
module top;
int a, b, c, d;
ap_abc: assert property(@ (a==1) b==2 |-> d==3 );
ap_abc2: assert property(@ (a==1) b==2 |-> @(b==5) d==4 );
// Note: some functions require a clocking event
$rose ( expression [, [clocking_event] ] )
$fell ( expression [, [clocking_event] ] )
$stable ( expression [, [clocking_event] ] )
$changed ( expression [ , [ clocking_event ] ] )
$past ( expression1 [, [number_of_ticks ] [, [expression2 ] [, [clocking_event]]] ] )
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
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- SVA in a UVM Class-based Environment
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