Assertion triggered by posedge of internal clock recognizing 0 -> X transition as posedge

SystemVerilog
,
1

Hi,

My frequency measure assertion as below, is measuring frequency even at 0 to X transition.

property property_name;
@(posedge TB.top_block.sub_block.clk)
frequency measuring content for above internal clock
endproperty

since, it is an internal signal. Im not sure if i should assign this clock signal to a bit variable and use that for trigger.
Wont it take some delay and cause deviation in frequency measure.

2

In reply to Adarsh Santhosh:

Assigning clk to a bit variable will not add any delay unless you explicitly add a delay.

3

In reply to dave_59:

I tried it and it works for me.
But, how does the GLS tool consider 0 → X transition as a posedge though?

i understand that 0/1/z/x may be valid values for non-bit type. but, still why does it consider as a posedge something other than low to high?

4

In reply to Adarsh Santhosh:

Because it was the easiest to implement. Verilog is either too pessimistic or too optimistic in dealing with X propagation. It was never designed to handle X’s properly in simulation.