/*
design view:
I am having 27 fifo (out_fifo and infifo);
# out_fifo is sending
# infifo is receiving
1) assertion to check that the transfer(out_fifo to infifo) is completed within 16 clock cycle.
2) as said, the same out_fifo should not send to its own infifo
testbench view:
I am having 27 agent (driver and monitor);
# driver is sending
# monitor is receiving
1) assertion to check that the transfer(driver to monitor) is completed within 16 clock cycle.
2) as said, the same driver should not send to its own monitor (same driver to same monitor)
*/
module assert_duration;
input clk, reset;
input in_rdy, in_vld; // used to received if both are high
input o_rdy, o_vld; // used to send if both are high
input [63:0] o_data [26:0]; // [57:0] =data [63:58] = dst_addr
input [63:0] i_data [26:0]; // [57:0] =data [63:58] = src_addr
// internal signals
bit [57:0] o_assert_data[26:0];
bit [57:0] i_assert_data[26:0];
bit [5:0] dst_addr [26:0];
bit [5:0] src_addr [26:0];
bit assert_en;
property data_transfer_p(bit o_vld, bit o_rdy, bit [57:0] i_assert_data, bit assert_en, bit [57:0] o_assert_data);
@(posedge of clk) iff (o_vld && o_rdy && assert_en) |-> ##[1:16] (o_assert_data == i_assert_data);
endpropery : data_transfer_p
// 2) assertion for if dst_addr is equal to src_addr it should not send data, (return error)
generate
for (genvar i =0; i <27; i ++)begin
initial begin
#1ns;
assert_en[i] = 1;
end
// data sending
always @(posedge clk iff reset) begin
if( o_vld && o_rdy) begin
o_assert_data[i] = o_data[57:0][i];
dst_addr[i] = o_data [63:58][i];
end
end
// data receiving
always @(posedge clk iff reset) begin
if( i_vld && i_rdy) begin
i_assert_data[i] = i_data[57:0][i];
src_addr[i] = i_data[63:58][i];
end
end
// assert
data_transfer_chk:assert property(data_transfer_p(.o_vld (o_vld[i]), .o_rdy(o_rdy[i]), .i_assert_data(i_assert_data[i], .assert_en(assert_en[i]), o_assert_data(o_assert_data[i]) )))
else begin
`uvm_error("data_transfer_chk",$sformatf("FAILED:%t",$realtime))
end
// if dst_addr is equal to src_addr check
end
engenerate
endmodule :assert_duration
I am new to assertions, need help to write for these scenarios, TIA!