Assertion for statistics

SystemVerilog
, ,
1

I have the following interfaces:

interface tx_in_interface (input bit clk, input bit tx_srstn);
   //dut input
   logic [15:0] xi;   
   logic [15:0] xq;   
   logic [15:0] sin;  
   logic [15:0] cos;  
   int 	chind2;   
endinterface

interface tx_out_interface (input bit clk, input bit tx_srstn);
   //dut output
   logic [15:0] y;
   int chind2;   
endinterface

I want to check that every time sin equal to 1(dec) y will be xi/sqrt(2), and every time cos equal to 1(dec) y will be xq/sqrt(2)

Can I do it with a specific kind of systemVerilog assertion (with no use of scoreboard or coverage)?

2

In reply to saritr:
You can use an immediate assertion. However, you need to identify your variables by their instances. Thus,


module m; 
  bit clk, tx_srstn;
  tx_in_interface  tx_in1(.*); 
  tx_out_interface tx_out1(.*);
  // NOT sure if you ned to type cast the sqrt.  If so, then 
 typedef logic [15:0] WORD;
  // I want to check that every time sin equal to 1(decimal) y will be xi/sqrt(2), 
  always if(tx_in1.sin==4'H0001) 
         a_sin: assert(tx_out1.y == WORD'(tx_in1.xi/(2 ** 0.5)) ); 
  // see 1800'2012 11.4.3 Arithmetic operators 

 //and every time cos equal to 1(dec) y will be xq/sqrt(2) 
 always if(tx_in1.cos==4'H0001) 
          a_cos: assert(tx_out1.y == WORD'(tx_in1.xq /(2 ** 0.5)) );

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

3

In reply to ben@SystemVerilog.us:

Is there any way to do it from one of the interface?

4

In reply to saritr:

In reply to ben@SystemVerilog.us:
Is there any way to do it from one of the interface?

Yes, assertions can be instantiated in modules, interfaces, checkers (1800 checker), programs. However, you must access the variables used in the assertions.
You declared 2 separate interfaces. If that is a requirement, then, you could in one of those interfaces, create an instance of the other interface. However, Why can’t you have just ONE interface, why do you really need TWO? If one interface, then all the variables used in the assertion are directly accessible from within the interface. Obviously, the assertion will only fire when the interface is instantiated somewhere. Thus,


interface tx_if (input bit clk, input bit tx_srstn);
   //dut input
   logic [15:0] xi;   
   logic [15:0] xq;   
   logic [15:0] sin;  
   logic [15:0] cos;  
   int 	chind2; 
   //dut output
   logic [15:0] y;
// NOT sure if you need to type cast the sqrt.  If so, then 
 typedef logic [15:0] WORD;
  // I want to check that every time sin equal to 1(decimal) y will be xi/sqrt(2), 
  always if(sin==4'H0001) 
         a_sin: assert(y == WORD'(xi/(2 ** 0.5)) ); 
  // see 1800'2012 11.4.3 Arithmetic operators 
 
 //and every time cos equal to 1(dec) y will be xq/sqrt(2) 
 always if(cos==4'H0001) 
          a_cos: assert(y == WORD'(xq /(2 ** 0.5)) ); 
endinterface

Ben ben@systemverilog.us

5

In reply to ben@SystemVerilog.us:

I have two intrefaces because each one of them “describe” different block in the design.
Can you give me example hot to do it in one of the interfaces?

6

In reply to saritr:


interface tx_in_interface (input bit clk, input bit tx_srstn);
   //dut input
   logic [15:0] xi;   
   logic [15:0] xq;   
   logic [15:0] sin;  
   logic [15:0] cos;  
   int 	chind2;   
   // Add an instance of tx_out <<-----------------------------------------
   tx_out_interface tx_out1(.*);
   typedef logic [15:0] WORD;
   // I want to check that every time sin equal to 1(decimal) y will be xi/sqrt(2), 
   always if(sin==4'H0001) 
         a_sin: assert(tx_out1.y == WORD'(xi/(2 ** 0.5)) ); 
   // see 1800'2012 11.4.3 Arithmetic operators 
 
   //and every time cos equal to 1(dec) y will be xq/sqrt(2) 
   always if(cos==4'H0001) 
          a_cos: assert(tx_out1.y == WORD'(xq /(2 ** 0.5)) ); 
endinterface
 
interface 
   //dut output
   logic [15:0] y;
   int chind2;   
endinterface

Ben systemverilog.us

7

In reply to ben@SystemVerilog.us:
The following code compiles and simulates.


import uvm_pkg::*; `include "uvm_macros.svh" 
interface tx_in_interface (input bit clk, input bit tx_srstn);
	//dut input
	logic [15:0] xi;   
	logic [15:0] xq;   
	logic [15:0] sin=16'H001;  
	logic [15:0] cos=16'H001;  
	int 	chind2;   
	// Add an instance of tx_out <<-----------------------------------------
	tx_out_interface tx_out1(.*);
	typedef logic [15:0] WORD;
	// I want to check that every time sin equal to 1(decimal) y will be xi/sqrt(2), 
	always @(posedge clk) if(sin==16'H0001) 
			a_sin: assert(tx_out1.y == WORD'(xi/(2 ** 0.5)) ); 
				// see 1800'2012 11.4.3 Arithmetic operators 
 
		//and every time cos equal to 1(dec) y will be xq/sqrt(2) 
	always @(posedge clk) if(cos==16'H0001) 
			a_cos: assert(tx_out1.y == WORD'(xq /(2 ** 0.5)) ); 
endinterface
 
interface tx_out_interface (input bit clk, input bit tx_srstn);
	//dut output
	logic [15:0] y;
	int chind2;   
endinterface

module top; 
	bit clk; 
	logic [15:0] xi;   
	logic [15:0] xq;   
	logic [15:0] sin;  
	logic [15:0] cos;  
	bit tx_srstn;
	int 	chind2;   
	default clocking @(posedge clk); endclocking
	initial forever #10 clk=!clk; 
	tx_in_interface tx_in0(.*); 
	tx_out_interface tx_out0(.*); 
	initial begin 
		#100 tx_in0.xi = 16'H0020; 
		tx_in0.xq=16'H0100; 
		tx_in0.tx_out1.y = 16'H0044;
		#200;
	end		
endmodule 
// SIMULATION 
** Error: Assertion error.
#    Time: 10 ns  Scope: top.tx_in0.a_sin File: ifc1.sv Line: 14
# ** Error: Assertion error.
#    Time: 10 ns  Scope: top.tx_in0.a_cos File: ifc1.sv Line: 19
# ** Error: Assertion error.
...

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us