Assertion sequence of events at variable time delay

SystemVerilog
,
1

Hi all, I’m very new to SVA and I’m kind of learning by doing.
I have a sequence I’d like to check with an assertion but I’m a bit lost. The idea is to verify the sequence of two interrupts. In a known DUT configuration we expect that IRQ1 shall be followed, in a variable amount of time but less than T, by an IRQ2. If IRQ1 repeats without the presence of IRQ2 than it is a mistake in the design.

So far I’m stuck with expressing the “variable amount of time but less than T” part and so far I got to this point:


sequence synchronization;
    IRQ1 ##[*:max] !IRQ1 and IRQ2;
endsequence

Unfortunately it doesn’t seem to be correct and I don’t really know how to express the behavior I expect.
Any pointer in the right direction is appreciated.

Al

2

Hi,

You can use this :

sequence synchronization;
    IRQ1 => !(IRQ1)[*1:max] intersect (IRQ2 [->1]);
endsequence

Bests
Irshad

3

In reply to Mohammed Irshad:

Hi,
You can use this :

sequence synchronization;
IRQ1 => !(IRQ1)[*1:max] intersect (IRQ2 [->1]);
endsequence

Bests
Irshad

Thanks for the hint! I wasn’t really thinking about intersecting two booleans, but it makes sense.