Assertion for reset synchronizer

I want to write an assertion checker for synchronization of reset.In the below snap when dss_reset_in is de-asserted then after 4 clock cycles dss_reset_out to be de-asserted. Another thing i want to state here that this 4 clock cycle is a variable. I mean user will set after how many clock cycles dss_reset_out to be de-asserted after de-assertion of dss_reset_in.

In reply to SUBHAM RAY SINGH:
The simplest way to handle dynamic repeats, range repeats, delays, and range delays is to use my SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy


module top;    
    import uvm_pkg::*; `include "uvm_macros.svh" 
    import sva_delay_repeat_range_pkg::*;
    bit clk, dss_reset_in, dss_reset_out;  
    int d1=4;  
    initial forever #10 clk=!clk;  
    //when dss_reset_in is de-asserted then after 4 clock cycles dss_reset_out to be de-asserted. 
    // ******       DYNAMIC DELAY ##d1 **********
    // Application:  $rose(a)  |-> q_dynamic_delay(d1) ##0 my_sequence;
    ap_dyn_delay: assert property(@ (negedge dss_reset_in) 1'b1 ##1
      @(posedge clk) q_dynamic_delay(d1) ##0 dss_reset_out==1'b0);

      always @(posedge dss_reset_in) begin
        dss_reset_out <= 1'b1;
        repeat(4) @(posedge clk);
        dss_reset_out <= 1'b0;
      end

      initial begin
        bit a; 
        bit[2:0] c;
        repeat (100) begin
          @(posedge clk);
          if (!randomize(a, c) with {
            a dist {1'b1 := 1, 1'b0 := 10};
            c inside {[3:6]}; 
          })
            `uvm_error("MYERR", "This is a randomize error");
           if(a) begin 
            d1 <= c; 
            #2 dss_reset_in <= 1'b1; 
            #2 dss_reset_in <= 1'b0; 
           end
        end
        $finish;
      end
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448

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