Hi I require help for this problem - The select signal goes high after every 3 clock cycles or will give an error.
It may be easy but I am really having trouble getting an answer.
Thank you
In reply to Vanshika Chawla:
You need some support logic.
My testbench needs improvement :)
//import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, a, b, e3, select;
int count;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
always_ff @(posedge clk) begin
count<=(count+1) % 3;
$display("count= %d", count);
end
ap: assert property(count==0 |-> ##3 select ##1 !select[*2])
$display("%t ap pass count=%d, select=", $realtime, $sampled(count), $sampled(select));
else $display("%t ap FAIL count=%d, select=", $realtime, $sampled(count), $sampled(select));
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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In reply to Vanshika Chawla:
property chkr;
@(posedge clk)
$rose(req) |=> !req[*3] ##1 $rose(req);
endproperty
test it here
I have setup a tb with a positive and a negative case…