Assertion property for busarbiter reset

Hi all,
I would like to know how can i verify the reset property of of the arbiter.

Arbiter input signals:
clk: std_logic – clock signal
reset: std_logic – reset signal (active high)
bus_req: std_logic_vector(2 downto 0) – requests by masters
ack: std_logic – from slave, signaling completion of transaction
Arbiter output signals:
bus_grant: std_logic_vector(2 downto 0) – grant signals, one for each master

In reply to nehjo:

The definition of bus signals is not a specification of the requirements.
You need to define, in English, what do you expect to happen (in cycles) when reset is in the active state.