Assertion not triggering

SystemVerilog
1

Hi All ,
I have written one assertion , but unfortunately I am not seeing it triggering. It is always in NA mode . I am missing a small stuff some where . Please guide .

Requirement as :-

  • I have to check the period for clock say CLK.
  • Assertion should be checked when txreset and rx reset are low.
  • Assertion should be checked when Ack goes high.

I have to check the period for clock say CLK.

Code written as :-
Declarations :—
reg CLK ; assign CLK =…;
reg ack ; assign ack = … ;
reg tx_reset ; assign tx_reset = …;
reg rx_reset; assign rx_reset = …;

time t1 ;
time t2 ;
time period_T;

always (@posedge CLK or rx_reset or tx_reset)

begin
if (!rx_reset || !tx_reset) begin

 t1 <= 0;
 t2 <= 0;
 period_T <= 0; 
end
else begin
t2 =  t1 ; 
t1 = $time;
period_T = t1 - t2 ;
end
end 

property CLK_FREQ; 
@(posedge CLK ) disable iff (rx_reset || tx_reset )
($rose (ack)) |-> ((Period_T >= 0.95 * 1715) && (Period_T <= 1.05 * 1715));
endproperty  

Freq_chk: assert property (CLK_FREQ)
            else begin
              $sformat(msg, "%t: %m: ERROR ........ ")
            end

NOTE: have to check Frequency of around 583 MHz, so period will 1715ps

Code is compiled clean , but still I am not seeing any trigger mechanism working . Need inputs.

Regards

2

In reply to arpkum:

I guess these have to be active low

@(posedge CLK ) disable iff (rx_reset || tx_reset )

3

In reply to srbeeram:

Hi srbeeram,
reset signals are active high .
Any other input .
thanks

4

In reply to arpkum:

if you show the complete code then it would be helpful.

if reset signals are active high,in your code you are applying reset when they are active low.

begin
if (!rx_reset || !tx_reset) begin

t1 <= 0;
t2 <= 0;
period_T <= 0;
end

5

In reply to srbeeram:

That is because i don’t want to tap the clock period when reset is applicable .