In reply to Jeff_Li_90:
Quote:
upon detected assertion, sequence detector fsm would return to initial stage, so it's safe to kill current thread and make it vacuous I think
bit detected;
@(posedge clk) sync_accept(detected) sequence_in ##1 sequence_in ##1 !sequence_in ##1 sequence_in |=> detected;
I presume that you have an FSM that sets/resets the bit detected.
The assertion as you wrote would not compile because the ! in !sequence_in is a logical operator. You cannot use the not in ... ##1 sequence_in ##1 not(sequence_in) because the not is a property operator. To fix that you can write
sequence_in ##1 sequence_in ##4 !sequence_in.triggered ##1 sequence_in |=> detected;
Now on the accept_on. !800'2017 says:
The accept_on/reject_on family of operators just terminates the property as an accept (true vacuously, with no contribution to the pass statistics) or reject (false vacuously, with contributions to the failed statistics).
The accept_on (expression_or_dist) property_expr accepts the property as true if the expression_or_dist (called the abort condition) is true. Otherwise, with the abort condition as false, the property expression evaluates to completion. The abort condition with the accept_on is asynchronous, whereas the sync_accept_on is synchronous to the clock under current consideration for the property. Unlike disable iff, the synchronous abort condition is sampled during the Preponed sampling region for properties.
You do not need it in this case, as it does nothing for you. All it does for you is kill the first attempt after detected==1. At every clocking event you start evaluating the sequence:
sequence_in ##1 sequence_in ##4 !sequence_in.triggered ##1 sequence_in
Here is an example of the accept_on. Note that when done occurs at any time, even within the repetition cycles, the assertion is true.
ap_accept_disable : assert property (@ (posedge clk)
disable iff (!reset_n)
sync_accept_on ( done )
$rose(dma_req) |=> data_transfer[*100]);
Ben Cohen
http://www.systemverilog.us/
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