In reply to ben@SystemVerilog.us:
Yes Ben, we should get an ack after req and also clk-signal toggles.
requirement are:
- after req asserted, followed by at least 3 clk prior to ack assertion
- after req de-asserted, ack should also de-assert and followed by at least 3 clk pulses before clk off
- residue clk from previous req running in current req is allowed
this is a back to back req, that's why we saw previous clk running in current req.
this clk is a signal , it's not the sampling clock (few GHz).
I was thinking to write this, but obviously it's not going to work:
assert_b2b_check_missing_ack: assert property (@(posedge sampling_clock) b2b_check_missing_ack));
property b2b_check_missing_ack;
//code here are conceptual only, it's not a working codes
@(posedge clk) $past(clk) == 0 |-> (##[0:$] changed(clk)) && req && !ack |-> !( (##[0:$] $stable(clk)) && req && !ack )
endproperty
the focus of the codes was to catch missing
ack throughout
clk start to stop running.
the difficulty here is that we have continuous stream of clk, req and ack. checking has to take care of the overlapping of all these signals.
